As is known, for several applications of microelectronics, a need has risen to integrate low-voltage devices and power devices (which operate at voltages that range from approximately 15 V to beyond 1000 V) in a single semiconductor chip. In particular, it has become increasingly more frequent to provide low-voltage devices in CMOS technology in a first portion of the chip and power devices, which are compatible with CMOS technology, in a second portion of the same chip. The active areas that house the various devices, both low-voltage devices and power devices, are insulated from one another using the shallow-trench insulation (STI) technique, which enables an extremely high degree of integration, with extremely small overall dimensions, and for this reason is typically used in CMOS technology. In practice, the substrate of a semiconductor wafer is selectively etched through a hard mask, for example, a multilayer mask of silicon oxide and silicon nitride, and trenches are formed, which delimit and separate active areas for low-voltage devices and active areas for power devices. The trenches are oxidized and completely filled with deposited dielectric, normally silicon oxide. The wafer is then planarized, and the hard mask is thus removed. The active areas are hence separated from one another by insulating structures with practically vertical walls, which extend for a stretch in the substrate.